Linear Current Starved Delay Element
نویسندگان
چکیده
Delay elements are basic building blocks of clock distribution network in VLSI circuits and systems. They are intended to define a time reference for the movement of data within those systems. In this paper, we describe an efficient structure of a linear current starved delay element. The proposal is based on modification of the bias circuit. Thanks to this modification, an improved linearity in delay variation is achieved. Simulation results that relate to 1.2 μm CMOS doublepoly double-metal technology show that the proposed current starved delay element has linear transfer function, i.e. linear delay in term of control voltage, in the full operating range of interest. Keyword – Bias circuit, delay, DLL, CMOS circuits design.
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